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RISCV 32-bit base and 64-bit extensions
I'd like to build a RISCV simulator in C language which would support a limited instruction set of the RISC-V ISA, restricted to the 32-bit base with 64- bit extensions (RV32I and RV64I). But I'm not quite understand what are the 64-bit extensions and how to use them. Could someone explain to me what the difference between the base and extensions and how could I distinguish them in code ?
c cpu-architecture riscv
asked Jan 1 at 17:24
BernBern
61
add a comment |
I'd like to build a RISCV simulator in C language which would support a limited instruction set of the RISC-V ISA, restricted to the 32-bit base with 64- bit extensions (RV32I and RV64I). But I'm not quite understand what are the 64-bit extensions and how to use them. Could someone explain to me what the difference between the base and extensions and how could I distinguish them in code ?
c cpu-architecture riscv
asked Jan 1 at 17:24
BernBern
61
1
Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28
add a comment |
I'd like to build a RISCV simulator in C language which would support a limited instruction set of the RISC-V ISA, restricted to the 32-bit base with 64- bit extensions (RV32I and RV64I). But I'm not quite understand what are the 64-bit extensions and how to use them. Could someone explain to me what the difference between the base and extensions and how could I distinguish them in code ?
c cpu-architecture riscv
asked Jan 1 at 17:24
BernBern
61
I'd like to build a RISCV simulator in C language which would support a limited instruction set of the RISC-V ISA, restricted to the 32-bit base with 64- bit extensions (RV32I and RV64I). But I'm not quite understand what are the 64-bit extensions and how to use them. Could someone explain to me what the difference between the base and extensions and how could I distinguish them in code ?
c cpu-architecture riscv
c cpu-architecture riscv
asked Jan 1 at 17:24
BernBern
61
asked Jan 1 at 17:24
BernBern
61
asked Jan 1 at 17:24
BernBern
61
asked Jan 1 at 17:24
BernBern
61
asked Jan 1 at 17:24
BernBern
61
61
1
Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28
add a comment |
1
Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28
1
1
Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28
Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28
add a comment |
1 Answer
1
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RISC-V is designed to support extensive customization and specialization. Each base instruction set is characterized by the width of the registers and the corresponding size of the user address space. There are two base variants, RV32I and RV64I, where I stands for integer ISA.
The base integer ISA may be subset by a hardware implementation, but opcode traps and software emulation by a supervisor layer must then be used to implement functionality not provided by hardware.
Although 64-bit address spaces are a requirement for larger systems, 32-bit address spaces may adequate for many embedded and client devices for decades to come and will be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces are sufficient for educational purposes. A larger flat 128-bit address space might eventually be required, so we could be accommodated within the RISC-V ISA framework.
The base integer ISA can be extended with one or more optional instruction-set extensions, however the base integer instructions cannot be redefined. RISC-V instruction-set extensions are divided into standard and non-standard extensions. Standard extensions should be generally useful and should not conflict with other standard extensions.
Non-standard extensions may be highly specialized, or may conflict with other standard or non-standard extensions.
Instruction-set extensions may provide slightly different functionality depending on the width of the base integer instruction set. A naming convention for RISC-V base instructions and instruction-set extensions, to support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arith- metic.
The base integer ISA is named “I” (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions, and is mandatory for all RISC-V implementations.
The standard integer multiplication and division extension is named “M”, and adds instructions to multiply and divide values held in the integer registers.
The standard atomic instruction extension, denoted by “A”, adds instructions that atomically read, modify, and write memory for inter-processor synchronization. The standard single-precision floating-point extension, denoted by “F”, adds floating-point registers, single-precision computational instructions, and single-precision loads and stores. The standard double-precision floating-point extension, denoted by “D”, expands the floating-point registers, and adds double precision computational instructions, loads, and stores.
Reference - RISC-V ISA Manual
answered Jan 1 at 17:50
sbhsbh
416
add a comment |
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1 Answer
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RISC-V is designed to support extensive customization and specialization. Each base instruction set is characterized by the width of the registers and the corresponding size of the user address space. There are two base variants, RV32I and RV64I, where I stands for integer ISA.
The base integer ISA may be subset by a hardware implementation, but opcode traps and software emulation by a supervisor layer must then be used to implement functionality not provided by hardware.
Although 64-bit address spaces are a requirement for larger systems, 32-bit address spaces may adequate for many embedded and client devices for decades to come and will be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces are sufficient for educational purposes. A larger flat 128-bit address space might eventually be required, so we could be accommodated within the RISC-V ISA framework.
The base integer ISA can be extended with one or more optional instruction-set extensions, however the base integer instructions cannot be redefined. RISC-V instruction-set extensions are divided into standard and non-standard extensions. Standard extensions should be generally useful and should not conflict with other standard extensions.
Non-standard extensions may be highly specialized, or may conflict with other standard or non-standard extensions.
Instruction-set extensions may provide slightly different functionality depending on the width of the base integer instruction set. A naming convention for RISC-V base instructions and instruction-set extensions, to support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arith- metic.
The base integer ISA is named “I” (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions, and is mandatory for all RISC-V implementations.
The standard integer multiplication and division extension is named “M”, and adds instructions to multiply and divide values held in the integer registers.
The standard atomic instruction extension, denoted by “A”, adds instructions that atomically read, modify, and write memory for inter-processor synchronization. The standard single-precision floating-point extension, denoted by “F”, adds floating-point registers, single-precision computational instructions, and single-precision loads and stores. The standard double-precision floating-point extension, denoted by “D”, expands the floating-point registers, and adds double precision computational instructions, loads, and stores.
Reference - RISC-V ISA Manual
answered Jan 1 at 17:50
sbhsbh
416
add a comment |
RISC-V is designed to support extensive customization and specialization. Each base instruction set is characterized by the width of the registers and the corresponding size of the user address space. There are two base variants, RV32I and RV64I, where I stands for integer ISA.
The base integer ISA may be subset by a hardware implementation, but opcode traps and software emulation by a supervisor layer must then be used to implement functionality not provided by hardware.
Although 64-bit address spaces are a requirement for larger systems, 32-bit address spaces may adequate for many embedded and client devices for decades to come and will be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces are sufficient for educational purposes. A larger flat 128-bit address space might eventually be required, so we could be accommodated within the RISC-V ISA framework.
The base integer ISA can be extended with one or more optional instruction-set extensions, however the base integer instructions cannot be redefined. RISC-V instruction-set extensions are divided into standard and non-standard extensions. Standard extensions should be generally useful and should not conflict with other standard extensions.
Non-standard extensions may be highly specialized, or may conflict with other standard or non-standard extensions.
Instruction-set extensions may provide slightly different functionality depending on the width of the base integer instruction set. A naming convention for RISC-V base instructions and instruction-set extensions, to support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arith- metic.
The base integer ISA is named “I” (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions, and is mandatory for all RISC-V implementations.
The standard integer multiplication and division extension is named “M”, and adds instructions to multiply and divide values held in the integer registers.
The standard atomic instruction extension, denoted by “A”, adds instructions that atomically read, modify, and write memory for inter-processor synchronization. The standard single-precision floating-point extension, denoted by “F”, adds floating-point registers, single-precision computational instructions, and single-precision loads and stores. The standard double-precision floating-point extension, denoted by “D”, expands the floating-point registers, and adds double precision computational instructions, loads, and stores.
Reference - RISC-V ISA Manual
answered Jan 1 at 17:50
sbhsbh
416
add a comment |
RISC-V is designed to support extensive customization and specialization. Each base instruction set is characterized by the width of the registers and the corresponding size of the user address space. There are two base variants, RV32I and RV64I, where I stands for integer ISA.
The base integer ISA may be subset by a hardware implementation, but opcode traps and software emulation by a supervisor layer must then be used to implement functionality not provided by hardware.
Although 64-bit address spaces are a requirement for larger systems, 32-bit address spaces may adequate for many embedded and client devices for decades to come and will be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces are sufficient for educational purposes. A larger flat 128-bit address space might eventually be required, so we could be accommodated within the RISC-V ISA framework.
The base integer ISA can be extended with one or more optional instruction-set extensions, however the base integer instructions cannot be redefined. RISC-V instruction-set extensions are divided into standard and non-standard extensions. Standard extensions should be generally useful and should not conflict with other standard extensions.
Non-standard extensions may be highly specialized, or may conflict with other standard or non-standard extensions.
Instruction-set extensions may provide slightly different functionality depending on the width of the base integer instruction set. A naming convention for RISC-V base instructions and instruction-set extensions, to support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arith- metic.
The base integer ISA is named “I” (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions, and is mandatory for all RISC-V implementations.
The standard integer multiplication and division extension is named “M”, and adds instructions to multiply and divide values held in the integer registers.
The standard atomic instruction extension, denoted by “A”, adds instructions that atomically read, modify, and write memory for inter-processor synchronization. The standard single-precision floating-point extension, denoted by “F”, adds floating-point registers, single-precision computational instructions, and single-precision loads and stores. The standard double-precision floating-point extension, denoted by “D”, expands the floating-point registers, and adds double precision computational instructions, loads, and stores.
Reference - RISC-V ISA Manual
answered Jan 1 at 17:50
sbhsbh
416
RISC-V is designed to support extensive customization and specialization. Each base instruction set is characterized by the width of the registers and the corresponding size of the user address space. There are two base variants, RV32I and RV64I, where I stands for integer ISA.
The base integer ISA may be subset by a hardware implementation, but opcode traps and software emulation by a supervisor layer must then be used to implement functionality not provided by hardware.
Although 64-bit address spaces are a requirement for larger systems, 32-bit address spaces may adequate for many embedded and client devices for decades to come and will be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces are sufficient for educational purposes. A larger flat 128-bit address space might eventually be required, so we could be accommodated within the RISC-V ISA framework.
The base integer ISA can be extended with one or more optional instruction-set extensions, however the base integer instructions cannot be redefined. RISC-V instruction-set extensions are divided into standard and non-standard extensions. Standard extensions should be generally useful and should not conflict with other standard extensions.
Non-standard extensions may be highly specialized, or may conflict with other standard or non-standard extensions.
Instruction-set extensions may provide slightly different functionality depending on the width of the base integer instruction set. A naming convention for RISC-V base instructions and instruction-set extensions, to support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arith- metic.
The base integer ISA is named “I” (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions, and is mandatory for all RISC-V implementations.
The standard integer multiplication and division extension is named “M”, and adds instructions to multiply and divide values held in the integer registers.
The standard atomic instruction extension, denoted by “A”, adds instructions that atomically read, modify, and write memory for inter-processor synchronization. The standard single-precision floating-point extension, denoted by “F”, adds floating-point registers, single-precision computational instructions, and single-precision loads and stores. The standard double-precision floating-point extension, denoted by “D”, expands the floating-point registers, and adds double precision computational instructions, loads, and stores.
Reference - RISC-V ISA Manual
answered Jan 1 at 17:50
sbhsbh
416
answered Jan 1 at 17:50
sbhsbh
416
answered Jan 1 at 17:50
sbhsbh
416
answered Jan 1 at 17:50
sbhsbh
416
416
add a comment |
add a comment |
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Have you read the documentation? What does it say about the matter?
– Some programmer dude
Jan 1 at 17:28