Mixing
VHDL - ror and rol operations
How can I solve this problem?
reg variable is defined as:
signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";
There is a problem with ror operation in the code below. The error message is:
Line 109: Syntax error near "ror".
Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
--
process(clk1,up_down,enable,reset)
begin
if up_down="1" then
reg ror 1;
end if;
end process;
syntax vhdl xilinx
asked Nov 20 '18 at 8:56
kaann45kaann45
94
add a comment |
How can I solve this problem?
reg variable is defined as:
signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";
There is a problem with ror operation in the code below. The error message is:
Line 109: Syntax error near "ror".
Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
--
process(clk1,up_down,enable,reset)
begin
if up_down="1" then
reg ror 1;
end if;
end process;
syntax vhdl xilinx
asked Nov 20 '18 at 8:56
kaann45kaann45
94
What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13
add a comment |
How can I solve this problem?
reg variable is defined as:
signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";
There is a problem with ror operation in the code below. The error message is:
Line 109: Syntax error near "ror".
Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
--
process(clk1,up_down,enable,reset)
begin
if up_down="1" then
reg ror 1;
end if;
end process;
syntax vhdl xilinx
asked Nov 20 '18 at 8:56
kaann45kaann45
94
How can I solve this problem?
reg variable is defined as:
signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";
There is a problem with ror operation in the code below. The error message is:
Line 109: Syntax error near "ror".
Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
--
process(clk1,up_down,enable,reset)
begin
if up_down="1" then
reg ror 1;
end if;
end process;
syntax vhdl xilinx
syntax vhdl xilinx
asked Nov 20 '18 at 8:56
kaann45kaann45
94
asked Nov 20 '18 at 8:56
kaann45kaann45
94
asked Nov 20 '18 at 8:56
kaann45kaann45
94
asked Nov 20 '18 at 8:56
kaann45kaann45
94
asked Nov 20 '18 at 8:56
kaann45kaann45
94
94
What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13
add a comment |
What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13
What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13
What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13
add a comment |
1 Answer
1
active
oldest
votes
Your problem is the the ror operator is not defined for std_logic_vector.
VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.
You have two solutions:
(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:
if up_down="1" then
reg <= reg(0) & reg(7 downto 1);
end if;
(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);
ror rol sla sra sll srl
By the way, this line would be wrong even if ror were defined for std_logic_vector:
reg ror 1;
You can't just say that any more than you could just say
reg + 1;
You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.reg ror 1is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).
– user1155120
Nov 20 '18 at 10:07
add a comment |
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1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
Your problem is the the ror operator is not defined for std_logic_vector.
VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.
You have two solutions:
(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:
if up_down="1" then
reg <= reg(0) & reg(7 downto 1);
end if;
(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);
ror rol sla sra sll srl
By the way, this line would be wrong even if ror were defined for std_logic_vector:
reg ror 1;
You can't just say that any more than you could just say
reg + 1;
You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.reg ror 1is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).
– user1155120
Nov 20 '18 at 10:07
add a comment |
Your problem is the the ror operator is not defined for std_logic_vector.
VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.
You have two solutions:
(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:
if up_down="1" then
reg <= reg(0) & reg(7 downto 1);
end if;
(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);
ror rol sla sra sll srl
By the way, this line would be wrong even if ror were defined for std_logic_vector:
reg ror 1;
You can't just say that any more than you could just say
reg + 1;
You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.reg ror 1is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).
– user1155120
Nov 20 '18 at 10:07
add a comment |
Your problem is the the ror operator is not defined for std_logic_vector.
VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.
You have two solutions:
(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:
if up_down="1" then
reg <= reg(0) & reg(7 downto 1);
end if;
(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);
ror rol sla sra sll srl
By the way, this line would be wrong even if ror were defined for std_logic_vector:
reg ror 1;
You can't just say that any more than you could just say
reg + 1;
You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
Your problem is the the ror operator is not defined for std_logic_vector.
VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.
You have two solutions:
(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:
if up_down="1" then
reg <= reg(0) & reg(7 downto 1);
end if;
(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);
ror rol sla sra sll srl
By the way, this line would be wrong even if ror were defined for std_logic_vector:
reg ror 1;
You can't just say that any more than you could just say
reg + 1;
You need to assign the result of the operation in both cases to something. I have assumed you want to assign it to reg in both cases.
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
answered Nov 20 '18 at 9:07
Matthew TaylorMatthew Taylor
7,1612731
7,1612731
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.reg ror 1is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).
– user1155120
Nov 20 '18 at 10:07
add a comment |
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.reg ror 1is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).
– user1155120
Nov 20 '18 at 10:07
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.
reg ror 1 is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).– user1155120
Nov 20 '18 at 10:07
The corresponding sequence of statements is executed for a condition returning TRUE in an if statement.
reg ror 1 is a shift expression not a sequential statement (IEEE Std 1076-2008 10.8 If statement, 9. Expressions, 9.1 shift_expression, 9.2.4 Shift operators, 10. Sequential statements). Without knowing the type of up_down you can tell "1" isn't of that type. The equality operator (9.2.3 Relational operators) is defined for all types other than file and protected types. The type of a string literal is determined by context and shall be a single dimensional array type (9.3.2 Literals).– user1155120
Nov 20 '18 at 10:07
add a comment |
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What is the type of up_down? The string literal "1" is not of that type. For each type declaration other than file and protected types there's an equality ("=") and inequality operator "/=" defined. A string literal's type is from context and must be a single dimensional array type with character enumeration elements (such as string, std_ulogic_vector, etc). Without a Minimal, Complete, and Verifiable example a fix isn't apparent for the line 108 error.
– user1155120
Nov 20 '18 at 10:13