Mixing
Compiling and linking subfolders using different Makefiles
I have a client/server application in C. The server has its own folder dserver, the same for the client dclient. Using both of them some files containing utility functions, I created another directory at the same level of the previously ones, named common.
My idea is to create each Makefile in each subfolder (one in dserver, one in dclient and another in common) and then one Makefile in the main directory which will run the other Makefiles which looks like:
all:
+$(MAKE) -C common
+$(MAKE) -C dserver
+$(MAKE) -C dclient
The first problem is that the common/Makefile should not create an executable but only create the object files that will be needed to create the executable for the client and for the server. In my case it is:
CXX = gcc
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $@
$(OBJDIR):
mkdir -p $(OBJDIR)
My problem is that it is creating the object directory specified by OBJDIR but not the object files *.o: how should it be?
Secondly in the client and server Makefiles I should both include path to the files in common and then referencing the object files in the resulting from the compilation of common to build the executables. So taking for example the dserver/Makefile I added the line INC_PATH = -I../common/ and referencing it in the compilation as $(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@. However in the code I had to do #include "../common/utilities.h".
Is there a way to include the path in the Makefile so that in the code it allows to do just: #include "utilities.h"?
And also, supposing that common has its own object directory containing the object files needed both by the client and server, how build, for example the server executable referencing the object files both in the common directory and the ones specific and contained in the server directory?
The dserver/Makefile is something like (and the dclient/Makefile has the same structure):
CXX = gcc
INC_PATH = -I../common/
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=./obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: server
clean:
$(RM) $(OBJECTS) $(DEPENDS) server
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
../server: $(OBJECTS)
$(CXX) $(WARNING) $(INC_PATH) $^ -o $@
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $@ $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@
c makefile compilation
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
add a comment |
I have a client/server application in C. The server has its own folder dserver, the same for the client dclient. Using both of them some files containing utility functions, I created another directory at the same level of the previously ones, named common.
My idea is to create each Makefile in each subfolder (one in dserver, one in dclient and another in common) and then one Makefile in the main directory which will run the other Makefiles which looks like:
all:
+$(MAKE) -C common
+$(MAKE) -C dserver
+$(MAKE) -C dclient
The first problem is that the common/Makefile should not create an executable but only create the object files that will be needed to create the executable for the client and for the server. In my case it is:
CXX = gcc
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $@
$(OBJDIR):
mkdir -p $(OBJDIR)
My problem is that it is creating the object directory specified by OBJDIR but not the object files *.o: how should it be?
Secondly in the client and server Makefiles I should both include path to the files in common and then referencing the object files in the resulting from the compilation of common to build the executables. So taking for example the dserver/Makefile I added the line INC_PATH = -I../common/ and referencing it in the compilation as $(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@. However in the code I had to do #include "../common/utilities.h".
Is there a way to include the path in the Makefile so that in the code it allows to do just: #include "utilities.h"?
And also, supposing that common has its own object directory containing the object files needed both by the client and server, how build, for example the server executable referencing the object files both in the common directory and the ones specific and contained in the server directory?
The dserver/Makefile is something like (and the dclient/Makefile has the same structure):
CXX = gcc
INC_PATH = -I../common/
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=./obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: server
clean:
$(RM) $(OBJECTS) $(DEPENDS) server
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
../server: $(OBJECTS)
$(CXX) $(WARNING) $(INC_PATH) $^ -o $@
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $@ $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@
c makefile compilation
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17
add a comment |
I have a client/server application in C. The server has its own folder dserver, the same for the client dclient. Using both of them some files containing utility functions, I created another directory at the same level of the previously ones, named common.
My idea is to create each Makefile in each subfolder (one in dserver, one in dclient and another in common) and then one Makefile in the main directory which will run the other Makefiles which looks like:
all:
+$(MAKE) -C common
+$(MAKE) -C dserver
+$(MAKE) -C dclient
The first problem is that the common/Makefile should not create an executable but only create the object files that will be needed to create the executable for the client and for the server. In my case it is:
CXX = gcc
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $@
$(OBJDIR):
mkdir -p $(OBJDIR)
My problem is that it is creating the object directory specified by OBJDIR but not the object files *.o: how should it be?
Secondly in the client and server Makefiles I should both include path to the files in common and then referencing the object files in the resulting from the compilation of common to build the executables. So taking for example the dserver/Makefile I added the line INC_PATH = -I../common/ and referencing it in the compilation as $(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@. However in the code I had to do #include "../common/utilities.h".
Is there a way to include the path in the Makefile so that in the code it allows to do just: #include "utilities.h"?
And also, supposing that common has its own object directory containing the object files needed both by the client and server, how build, for example the server executable referencing the object files both in the common directory and the ones specific and contained in the server directory?
The dserver/Makefile is something like (and the dclient/Makefile has the same structure):
CXX = gcc
INC_PATH = -I../common/
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=./obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: server
clean:
$(RM) $(OBJECTS) $(DEPENDS) server
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
../server: $(OBJECTS)
$(CXX) $(WARNING) $(INC_PATH) $^ -o $@
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $@ $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@
c makefile compilation
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
I have a client/server application in C. The server has its own folder dserver, the same for the client dclient. Using both of them some files containing utility functions, I created another directory at the same level of the previously ones, named common.
My idea is to create each Makefile in each subfolder (one in dserver, one in dclient and another in common) and then one Makefile in the main directory which will run the other Makefiles which looks like:
all:
+$(MAKE) -C common
+$(MAKE) -C dserver
+$(MAKE) -C dclient
The first problem is that the common/Makefile should not create an executable but only create the object files that will be needed to create the executable for the client and for the server. In my case it is:
CXX = gcc
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $@
$(OBJDIR):
mkdir -p $(OBJDIR)
My problem is that it is creating the object directory specified by OBJDIR but not the object files *.o: how should it be?
Secondly in the client and server Makefiles I should both include path to the files in common and then referencing the object files in the resulting from the compilation of common to build the executables. So taking for example the dserver/Makefile I added the line INC_PATH = -I../common/ and referencing it in the compilation as $(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@. However in the code I had to do #include "../common/utilities.h".
Is there a way to include the path in the Makefile so that in the code it allows to do just: #include "utilities.h"?
And also, supposing that common has its own object directory containing the object files needed both by the client and server, how build, for example the server executable referencing the object files both in the common directory and the ones specific and contained in the server directory?
The dserver/Makefile is something like (and the dclient/Makefile has the same structure):
CXX = gcc
INC_PATH = -I../common/
SOURCEDIR := ./
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=./obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: server
clean:
$(RM) $(OBJECTS) $(DEPENDS) server
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
../server: $(OBJECTS)
$(CXX) $(WARNING) $(INC_PATH) $^ -o $@
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $@ $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $(INC_PATH) $< -o $@
c makefile compilation
c makefile compilation
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
edited Jan 2 at 15:29
Francesco Boi
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
asked Jan 2 at 15:18
Francesco BoiFrancesco Boi
2,74022643
2,74022643
An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17
add a comment |
An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17
An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17
An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17
add a comment |
1 Answer
1
active
oldest
votes
You don't specify any rules for building the objects in your "common" Makefile - this is the only rule you have.
$(OBJDIR):
mkdir -p $(OBJDIR)
You want to put a rule before that to all get it to build the objects, maybe something along the lines of:
all: $(OBJDIR) $(OBJECTS)
It has to go before the original rule as if you don't specify what is being built, make will do the first rule it finds.
Including header files from "common" in your other directories should be working just fine by using -I../common/.
Using the objects from "common" should just be a case of adding them to the list of objects ie:
COMMON_OBJECTS=../common/obj/utilities.o
../server: $(OBJECTS) $(COMMON_OBJECTS)
Or having them built into a library so you don't need to know what object files there are.
Also it's worth noting that $(CXX) is the variable used to store the C++ compiler - for building with the C compiler you want to be using $(CC) and $(CFLAGS).
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
all: $(OBJDIR) $(OBJECTS)breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g.%.o : %.cc | $$(@D)(requires.SECONDEXPANSION).
– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS)is not working: it seems it is not linking properly: the error isundefined reference to FunctionInCommonFile
– Francesco Boi
Jan 2 at 17:33
You are right about the rule incommon/Makefilethough
– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
add a comment |
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1 Answer
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active
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votes
You don't specify any rules for building the objects in your "common" Makefile - this is the only rule you have.
$(OBJDIR):
mkdir -p $(OBJDIR)
You want to put a rule before that to all get it to build the objects, maybe something along the lines of:
all: $(OBJDIR) $(OBJECTS)
It has to go before the original rule as if you don't specify what is being built, make will do the first rule it finds.
Including header files from "common" in your other directories should be working just fine by using -I../common/.
Using the objects from "common" should just be a case of adding them to the list of objects ie:
COMMON_OBJECTS=../common/obj/utilities.o
../server: $(OBJECTS) $(COMMON_OBJECTS)
Or having them built into a library so you don't need to know what object files there are.
Also it's worth noting that $(CXX) is the variable used to store the C++ compiler - for building with the C compiler you want to be using $(CC) and $(CFLAGS).
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
all: $(OBJDIR) $(OBJECTS)breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g.%.o : %.cc | $$(@D)(requires.SECONDEXPANSION).
– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS)is not working: it seems it is not linking properly: the error isundefined reference to FunctionInCommonFile
– Francesco Boi
Jan 2 at 17:33
You are right about the rule incommon/Makefilethough
– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
add a comment |
You don't specify any rules for building the objects in your "common" Makefile - this is the only rule you have.
$(OBJDIR):
mkdir -p $(OBJDIR)
You want to put a rule before that to all get it to build the objects, maybe something along the lines of:
all: $(OBJDIR) $(OBJECTS)
It has to go before the original rule as if you don't specify what is being built, make will do the first rule it finds.
Including header files from "common" in your other directories should be working just fine by using -I../common/.
Using the objects from "common" should just be a case of adding them to the list of objects ie:
COMMON_OBJECTS=../common/obj/utilities.o
../server: $(OBJECTS) $(COMMON_OBJECTS)
Or having them built into a library so you don't need to know what object files there are.
Also it's worth noting that $(CXX) is the variable used to store the C++ compiler - for building with the C compiler you want to be using $(CC) and $(CFLAGS).
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
all: $(OBJDIR) $(OBJECTS)breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g.%.o : %.cc | $$(@D)(requires.SECONDEXPANSION).
– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS)is not working: it seems it is not linking properly: the error isundefined reference to FunctionInCommonFile
– Francesco Boi
Jan 2 at 17:33
You are right about the rule incommon/Makefilethough
– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
add a comment |
You don't specify any rules for building the objects in your "common" Makefile - this is the only rule you have.
$(OBJDIR):
mkdir -p $(OBJDIR)
You want to put a rule before that to all get it to build the objects, maybe something along the lines of:
all: $(OBJDIR) $(OBJECTS)
It has to go before the original rule as if you don't specify what is being built, make will do the first rule it finds.
Including header files from "common" in your other directories should be working just fine by using -I../common/.
Using the objects from "common" should just be a case of adding them to the list of objects ie:
COMMON_OBJECTS=../common/obj/utilities.o
../server: $(OBJECTS) $(COMMON_OBJECTS)
Or having them built into a library so you don't need to know what object files there are.
Also it's worth noting that $(CXX) is the variable used to store the C++ compiler - for building with the C compiler you want to be using $(CC) and $(CFLAGS).
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
You don't specify any rules for building the objects in your "common" Makefile - this is the only rule you have.
$(OBJDIR):
mkdir -p $(OBJDIR)
You want to put a rule before that to all get it to build the objects, maybe something along the lines of:
all: $(OBJDIR) $(OBJECTS)
It has to go before the original rule as if you don't specify what is being built, make will do the first rule it finds.
Including header files from "common" in your other directories should be working just fine by using -I../common/.
Using the objects from "common" should just be a case of adding them to the list of objects ie:
COMMON_OBJECTS=../common/obj/utilities.o
../server: $(OBJECTS) $(COMMON_OBJECTS)
Or having them built into a library so you don't need to know what object files there are.
Also it's worth noting that $(CXX) is the variable used to store the C++ compiler - for building with the C compiler you want to be using $(CC) and $(CFLAGS).
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
answered Jan 2 at 15:49
Chris TurnerChris Turner
7,31211118
7,31211118
all: $(OBJDIR) $(OBJECTS)breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g.%.o : %.cc | $$(@D)(requires.SECONDEXPANSION).
– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS)is not working: it seems it is not linking properly: the error isundefined reference to FunctionInCommonFile
– Francesco Boi
Jan 2 at 17:33
You are right about the rule incommon/Makefilethough
– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
add a comment |
all: $(OBJDIR) $(OBJECTS)breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g.%.o : %.cc | $$(@D)(requires.SECONDEXPANSION).
– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS)is not working: it seems it is not linking properly: the error isundefined reference to FunctionInCommonFile
– Francesco Boi
Jan 2 at 17:33
You are right about the rule incommon/Makefilethough
– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
all: $(OBJDIR) $(OBJECTS) breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g. %.o : %.cc | $$(@D) (requires .SECONDEXPANSION).– Maxim Egorushkin
Jan 2 at 16:15
all: $(OBJDIR) $(OBJECTS) breaks in parallel builds. The robust way is to have object files depend order-only on their directories. e.g. %.o : %.cc | $$(@D) (requires .SECONDEXPANSION).– Maxim Egorushkin
Jan 2 at 16:15
../server: $(OBJECTS) $(COMMON_OBJECTS) is not working: it seems it is not linking properly: the error is undefined reference to FunctionInCommonFile– Francesco Boi
Jan 2 at 17:33
../server: $(OBJECTS) $(COMMON_OBJECTS) is not working: it seems it is not linking properly: the error is undefined reference to FunctionInCommonFile– Francesco Boi
Jan 2 at 17:33
You are right about the rule in
common/Makefile though– Francesco Boi
Jan 2 at 17:33
You are right about the rule in
common/Makefile though– Francesco Boi
Jan 2 at 17:33
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@MaximEgorushkin That is already in the OP's Makefile
– Chris Turner
Jan 2 at 17:40
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
@FrancescoBoi that implies you've missed out one (or more) of the object files from common, or there is some code you've not yet written
– Chris Turner
Jan 2 at 17:42
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An example non-recursive make for you: stackoverflow.com/a/7321954/412080
– Maxim Egorushkin
Jan 2 at 16:17