RC Lowpass Filter between Amplifier and ADC input

I have sensors (pyranometers that consist of thermopiles and measure sun irradiation) that ouput a low voltage signal so I need to amplify them using an instrumentation amplifier.
I have chosen the AD8237 for this task: Datasheet

Im using a gain of 100 to amplify the initial low voltage signal (ranging 0-20mV) to 0-2V range.

Im then feeding the amplified signal to the ADC (MCP3422): Datasheet

My sensor values change very slowly and I will read out the digitized ADC values only once every second, so speed is not important in my case.

Now as pointed out in the accepted answer in this question I need a filter between the IN-Amp and the ADC to filter the noise.
In many ADC-datasheets a simple passive RC-filter is suggested between the INA and ADC.
I did quite some research and I still have some questions that confuse me and I hope you can help me with:

I figured that a first order RC filter does not meet my requirements so I cascaded multiple RC stages:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

And this is the simulated filter response in LTSpice:
rc_filter

Questions:

Can I do that? What would be the disadvantages using the proposed filter?
Capacitor values like 47µF or even 100µF give me a even better response (stronger attenuation), would that have a negative impact on my signal or the ADC?

I guess resistor values should not be further increased to prevent voltage drop on my signal?

The filter response seems very promising: Signals at 10Hz already attenuated by ~50% and at 25Hz already by ~90%. As I only care about the DC signal I guess that response should be fine (also 50-60Hz range is covered strongly by the filter).

Resistors create voltage drops so how would these three cascaded resistors affect my amplified signal (thus my digitized value calculated by the ADC)? Ohms law should apply, but I do not know the current...
Any clarification on this is highly appreciated.

Regarding speed/time constants: As my data acquisition (readout ADC once per second) and change in sensor value is very slow I do not need to keep an eye on the speed/time constant of this filter?

As many datasheets suggest an RC filter stage this approach should not be too far off?

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

$begingroup$
why not use LC filters?
$endgroup$
– atmnt
Jan 21 at 1:10

2

$begingroup$
mainly because I had to choose very very large values for L to get the same attenuation in the low Hz region. Feel free to suggest a configuration, I appreciate any help I can get! :)
$endgroup$
– Henry
Jan 21 at 1:32

add a comment |

Im using a gain of 100 to amplify the initial low voltage signal (ranging 0-20mV) to 0-2V range.

Im then feeding the amplified signal to the ADC (MCP3422): Datasheet

My sensor values change very slowly and I will read out the digitized ADC values only once every second, so speed is not important in my case.

I figured that a first order RC filter does not meet my requirements so I cascaded multiple RC stages:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

And this is the simulated filter response in LTSpice:
rc_filter

Questions:

I guess resistor values should not be further increased to prevent voltage drop on my signal?

Regarding speed/time constants: As my data acquisition (readout ADC once per second) and change in sensor value is very slow I do not need to keep an eye on the speed/time constant of this filter?

As many datasheets suggest an RC filter stage this approach should not be too far off?

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

$begingroup$
why not use LC filters?
$endgroup$
– atmnt
Jan 21 at 1:10

2

$begingroup$
mainly because I had to choose very very large values for L to get the same attenuation in the low Hz region. Feel free to suggest a configuration, I appreciate any help I can get! :)
$endgroup$
– Henry
Jan 21 at 1:32

add a comment |

Im using a gain of 100 to amplify the initial low voltage signal (ranging 0-20mV) to 0-2V range.

Im then feeding the amplified signal to the ADC (MCP3422): Datasheet

My sensor values change very slowly and I will read out the digitized ADC values only once every second, so speed is not important in my case.

I figured that a first order RC filter does not meet my requirements so I cascaded multiple RC stages:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

And this is the simulated filter response in LTSpice:
rc_filter

Questions:

I guess resistor values should not be further increased to prevent voltage drop on my signal?

Regarding speed/time constants: As my data acquisition (readout ADC once per second) and change in sensor value is very slow I do not need to keep an eye on the speed/time constant of this filter?

As many datasheets suggest an RC filter stage this approach should not be too far off?

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

Im using a gain of 100 to amplify the initial low voltage signal (ranging 0-20mV) to 0-2V range.

Im then feeding the amplified signal to the ADC (MCP3422): Datasheet

My sensor values change very slowly and I will read out the digitized ADC values only once every second, so speed is not important in my case.

I figured that a first order RC filter does not meet my requirements so I cascaded multiple RC stages:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

And this is the simulated filter response in LTSpice:
rc_filter

Questions:

I guess resistor values should not be further increased to prevent voltage drop on my signal?

Regarding speed/time constants: As my data acquisition (readout ADC once per second) and change in sensor value is very slow I do not need to keep an eye on the speed/time constant of this filter?

As many datasheets suggest an RC filter stage this approach should not be too far off?

amplifier adc filter instrumentation-amplifier passive-filter

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

edited Jan 21 at 1:02

asked Jan 21 at 0:49

Henry

768

asked Jan 21 at 0:49

Henry

768

asked Jan 21 at 0:49

Henry

768

$begingroup$
why not use LC filters?
$endgroup$
– atmnt
Jan 21 at 1:10

2

$begingroup$
mainly because I had to choose very very large values for L to get the same attenuation in the low Hz region. Feel free to suggest a configuration, I appreciate any help I can get! :)
$endgroup$
– Henry
Jan 21 at 1:32

add a comment |

$begingroup$
why not use LC filters?
$endgroup$
– atmnt
Jan 21 at 1:10

2

$begingroup$
mainly because I had to choose very very large values for L to get the same attenuation in the low Hz region. Feel free to suggest a configuration, I appreciate any help I can get! :)
$endgroup$
– Henry
Jan 21 at 1:32

why not use LC filters?

– atmnt
Jan 21 at 1:10

mainly because I had to choose very very large values for L to get the same attenuation in the low Hz region. Feel free to suggest a configuration, I appreciate any help I can get! :)

– Henry
Jan 21 at 1:32

add a comment |

6 Answers
6

active

oldest

votes

This 3-section RC should provide better rolloff at high frequencies. The random noise is dominated by that 3,000,000 ohm resistor with the 5Hz bandwidth, less than 1uV RMS.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Here is what Signal Chain Explorer (we used that to predict Gargoyles interferer levels)
shows as the 3-pole rolloff. With 2 volts PP input, the ENOB is 19.7

enter image description here

Notice we are NOT including ANY ADC noise contributions.

answered Jan 21 at 4:07

analogsystemsrf

15k2719

$begingroup$
Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?
$endgroup$
– Henry
Jan 22 at 22:55

1

$begingroup$
The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.
$endgroup$
– analogsystemsrf
Jan 29 at 3:02

$begingroup$
Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?
$endgroup$
– Henry
Jan 29 at 23:52

add a comment |

If you are reading the ADC just once per second then you need to eliminate frequencies above 0.5 Hz to prevent aliasing. If you think your system will have noise at, say 10 Hz, then that noise will contaminate your readings. I recommend that you sample at a much higher rate, perhaps some multiple of the power mains frequency, and perform low-pass filtering in software. Even a simple moving-average filter would work and wouldn't take much processing.

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

$begingroup$
So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?
$endgroup$
– Henry
Jan 21 at 14:13

$begingroup$
If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.
$endgroup$
– Elliot Alderson
Jan 21 at 14:17

$begingroup$
In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?
$endgroup$
– Henry
Jan 22 at 22:39

$begingroup$
Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...
$endgroup$
– Elliot Alderson
Jan 22 at 23:13

1

$begingroup$
But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".
$endgroup$
– Elliot Alderson
Jan 22 at 23:16

|
show 3 more comments

ADC inputs typically are quite high impedance. I have often used 100K in series with an input with no dc loss. (and a capacitor to ground for filtering) If you are happy with the attenuation with that circuit then I would suggest scaling the resistors up and the capacitors down. I would not use electrolytic capacitors as they tend to have more leakage compared to other types. I would probably use a ceramic cap.

Edit:

I just looked at the data sheet for the part. Go take a look at page 3, Input Impedance. Loading certainly will not be an issue.

answered Jan 21 at 1:49

Rudy

2616

$begingroup$
Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!
$endgroup$
– Henry
Jan 21 at 14:17

add a comment |

Your filter will effectively short out the amp if the signal has any significant AC component (even around mains frequency and first/second harmonic). Check out the datasheet: your amp has 4 mA short current and response characteristics are measured with loads of 10-100 kOhm. The equivalent resistance of your filter must be at least that big.

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

$begingroup$
So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?
$endgroup$
– Henry
Jan 21 at 17:03

$begingroup$
Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.
$endgroup$
– Henry
Jan 22 at 22:41

$begingroup$
@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.
$endgroup$
– Dmitry Grigoryev
Jan 23 at 8:31

$begingroup$
I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!
$endgroup$
– Henry
Jan 23 at 21:18

1

$begingroup$
ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.
$endgroup$
– Dmitry Grigoryev
Jan 24 at 15:19

|
show 4 more comments

The ADC input will look like a SHORT, for 5 or 10 nanoSeconds, at beginning of the Sample time. That "short" will disrupt any opamp directly connected to the ADC Vin or the ADC VREF.

To prevent this "disruption" (which shows up as ringing, and perhaps input-voltage-dependent quantization errors, we can place LARGE capacitors on the Vin and the VREF pins.

Assume the ADC has 10pF capacitors on its Vin and VREF pins, and assume these capacitors have had their charge consumed during the just-prior ADC operation.

As the ADC once again grabs some charge, there will be surge currents demanded from the external voltage sources(Vin and/or VREF).

To minimize the voltage upset, use LARGE external capacitors: 100X or 1,000X or 10,000X larger than the ADC sample (10pF) capacitors.

In the 3-cascaded_RC filter I gave you, that final capacitor is 10nF (10,000 pF) and should work well.

Again, if the AVERAGE input current is 9nanoAmps (Vin of 3 volts, Cap is 3pF, Fsample being 1,000 per second), flowing thru 3,000,000 ohms, there will be an error of 27 microvolts. This will show up as a linear gain error.

answered Jan 31 at 3:41

analogsystemsrf

15k2719

add a comment |

I agree with Elliot - a little different approach could be to sample/hold, sort of a Nyquist filter where you pick the best over-sample frequency to get rid of the most prevalent noise. I've done that with RTDs in a noisy aircraft and it gave me good results. I was dealing with millivolt changes that had to be very accurate. That gets rid of those big caps and the insertion loss from the resistors that you are concerned about.

I just threw this together in LTspice to give you the idea... if you want the source I will send it. I made the input the 2 volts which would include the amplifier in your design. I added 50Hz and some random HF noise riding on top of that.
Simulation of filter - LTspice

The filter uses active components except for the R/C tweak with filter 3. Implementation is up to the designer but this can be done with tiny parts, 2x2 to 4x4mm for most active and 0402s for the rest. I think that's smaller than the passive parts but if RE is important an area study is necessary. I just show a switch (S/H) for the concept. Once implemented a value change or two will adjust the sample rate.

From a practical viewpoint, the input is almost DC with such slow fluctuations. The noise is much faster and random with respects to the fixed sample rate so it averages out. The assumption is that the noise excursions fluctuate around zero, typical of differential coupling. I used this with RTDs which are slower and in an aircraft environment which is noisy (it qualified MIL-STD-461). It seems like it would do a good job for this source as well, but will take some tinkering based on the real world.

I displayed the parameters on the schematic so you can lift them if you use LTspice.

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

$begingroup$
sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.
$endgroup$
– Henry
Jan 21 at 12:21

$begingroup$
Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?
$endgroup$
– Henry
Jan 22 at 22:44

add a comment |

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6 Answers
6

active

oldest

votes

6 Answers
6

active

oldest

votes

This 3-section RC should provide better rolloff at high frequencies. The random noise is dominated by that 3,000,000 ohm resistor with the 5Hz bandwidth, less than 1uV RMS.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Here is what Signal Chain Explorer (we used that to predict Gargoyles interferer levels)
shows as the 3-pole rolloff. With 2 volts PP input, the ENOB is 19.7

enter image description here

Notice we are NOT including ANY ADC noise contributions.

answered Jan 21 at 4:07

analogsystemsrf

15k2719

$begingroup$
Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?
$endgroup$
– Henry
Jan 22 at 22:55

1

$begingroup$
The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.
$endgroup$
– analogsystemsrf
Jan 29 at 3:02

$begingroup$
Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?
$endgroup$
– Henry
Jan 29 at 23:52

add a comment |

This 3-section RC should provide better rolloff at high frequencies. The random noise is dominated by that 3,000,000 ohm resistor with the 5Hz bandwidth, less than 1uV RMS.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Here is what Signal Chain Explorer (we used that to predict Gargoyles interferer levels)
shows as the 3-pole rolloff. With 2 volts PP input, the ENOB is 19.7

enter image description here

Notice we are NOT including ANY ADC noise contributions.

answered Jan 21 at 4:07

analogsystemsrf

15k2719

$begingroup$
Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?
$endgroup$
– Henry
Jan 22 at 22:55

1

$begingroup$
The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.
$endgroup$
– analogsystemsrf
Jan 29 at 3:02

$begingroup$
Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?
$endgroup$
– Henry
Jan 29 at 23:52

add a comment |

This 3-section RC should provide better rolloff at high frequencies. The random noise is dominated by that 3,000,000 ohm resistor with the 5Hz bandwidth, less than 1uV RMS.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Here is what Signal Chain Explorer (we used that to predict Gargoyles interferer levels)
shows as the 3-pole rolloff. With 2 volts PP input, the ENOB is 19.7

enter image description here

Notice we are NOT including ANY ADC noise contributions.

answered Jan 21 at 4:07

analogsystemsrf

15k2719

This 3-section RC should provide better rolloff at high frequencies. The random noise is dominated by that 3,000,000 ohm resistor with the 5Hz bandwidth, less than 1uV RMS.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Here is what Signal Chain Explorer (we used that to predict Gargoyles interferer levels)
shows as the 3-pole rolloff. With 2 volts PP input, the ENOB is 19.7

enter image description here

Notice we are NOT including ANY ADC noise contributions.

answered Jan 21 at 4:07

analogsystemsrf

15k2719

answered Jan 21 at 4:07

analogsystemsrf

15k2719

answered Jan 21 at 4:07

analogsystemsrf

15k2719

answered Jan 21 at 4:07

analogsystemsrf

15k2719

$begingroup$
Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?
$endgroup$
– Henry
Jan 22 at 22:55

1

$begingroup$
The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.
$endgroup$
– analogsystemsrf
Jan 29 at 3:02

$begingroup$
Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?
$endgroup$
– Henry
Jan 29 at 23:52

add a comment |

$begingroup$
Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?
$endgroup$
– Henry
Jan 22 at 22:55

1

$begingroup$
The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.
$endgroup$
– analogsystemsrf
Jan 29 at 3:02

$begingroup$
Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?
$endgroup$
– Henry
Jan 29 at 23:52

Thank you very much! :) To make sure: I assume the box (including the 3pF cap and FET and R4) is modeling the ADC? Simulation of your filter in LTSpice is very promising, Im wondering how did you come up with the initial values? Hope you will share your approach. Do I see it right that this filtering will not have any negative inpact/voltage drop on my desired DC signal?

– Henry
Jan 22 at 22:55

The leftmost value is chosen to be a light load on the INA. Other resistors are simply scaled up 10X and 100X, to be light loads on the prior RC section, so the far-out attenuation is indeed 60dB/decade. The ADC must draw some charge. Rumor tells us there will be a DC voltage drop across the resistors. 3pF and 3volts and 1,000 sample/second have I = F * C * V = 9 nanoAmps average current; thru that 3MegOhm final resistor, the average DC offset will be 27 microVolts. To reduce, use 10Kohm, 47Kohm, 270Kohm.

– analogsystemsrf
Jan 29 at 3:02

Great explanation, thanks! Could you please tell me if Dmitry Grigoryev in his answer is right and I have to use at least 10-100 kOhm in the RC-filter? Would it be a problem to use only one stage of a single pole RC-filter with 1 kOhm and 10µF for testing. Could I damage my instrumentation amplifier with that?

– Henry
Jan 29 at 23:52

add a comment |

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

$begingroup$
So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?
$endgroup$
– Henry
Jan 21 at 14:13

$begingroup$
If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.
$endgroup$
– Elliot Alderson
Jan 21 at 14:17

$begingroup$
In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?
$endgroup$
– Henry
Jan 22 at 22:39

$begingroup$
Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...
$endgroup$
– Elliot Alderson
Jan 22 at 23:13

1

$begingroup$
But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".
$endgroup$
– Elliot Alderson
Jan 22 at 23:16

|
show 3 more comments

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

$begingroup$
So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?
$endgroup$
– Henry
Jan 21 at 14:13

$begingroup$
If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.
$endgroup$
– Elliot Alderson
Jan 21 at 14:17

$begingroup$
In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?
$endgroup$
– Henry
Jan 22 at 22:39

$begingroup$
Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...
$endgroup$
– Elliot Alderson
Jan 22 at 23:13

1

$begingroup$
But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".
$endgroup$
– Elliot Alderson
Jan 22 at 23:16

|
show 3 more comments

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

answered Jan 21 at 2:20

Elliot Alderson

7,45011022

$begingroup$
So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?
$endgroup$
– Henry
Jan 21 at 14:13

$begingroup$
If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.
$endgroup$
– Elliot Alderson
Jan 21 at 14:17

$begingroup$
In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?
$endgroup$
– Henry
Jan 22 at 22:39

$begingroup$
Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...
$endgroup$
– Elliot Alderson
Jan 22 at 23:13

1

$begingroup$
But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".
$endgroup$
– Elliot Alderson
Jan 22 at 23:16

|
show 3 more comments

$begingroup$
So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?
$endgroup$
– Henry
Jan 21 at 14:13

$begingroup$
If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.
$endgroup$
– Elliot Alderson
Jan 21 at 14:17

$begingroup$
In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?
$endgroup$
– Henry
Jan 22 at 22:39

$begingroup$
Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...
$endgroup$
– Elliot Alderson
Jan 22 at 23:13

1

$begingroup$
But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".
$endgroup$
– Elliot Alderson
Jan 22 at 23:16

So I could use the proposed filter in case I read out e.g. 10 times per second and perform averaging of these 10 values I got out of the ADC in software?

– Henry
Jan 21 at 14:13

If you sample at 10 times per second then all of the frequencies above 5 Hz in your input signal will be aliased. Is the noise content in your signal above 5 Hz low enough that you can live with the error due to aliasing? Only you can answer that question.

– Elliot Alderson
Jan 21 at 14:17

In order to use the 18Bit resolution mode, one has to set the ADC to 3.75 SPS (and I would read once per second, but I guess only the 3.75 samples per second rate is important here. Does it make a difference that im dealing with a delta sigma ADC here?). I'm a bit confused as I only need the DC signal (and that has no frequency?) so this aliasing issue still applies to me? If I use a modified version of the filter proposed above, with resistor values 1k and values for the caps 47µF I get an attenuation of ~-15dB at 3 Hz, so I should be fine in that case?

– Henry
Jan 22 at 22:39

Your statements are inconsistent. If you only need the dc signal then you only need to sample the signal once and never again. If you sample every second then it must be because the signal is changing, therefore it is not a dc signal. Furthermore, your signal will be noisy and this noise is an ac signal. So, your signal is an ac signal, not a dc signal. Therefore, you need to think about aliasing. The ADC does have an internal filter (see 4.7 in the datasheet) but it may not be enough...

– Elliot Alderson
Jan 22 at 23:13

But only you really know what your signal looks like and only you know what accuracy your system requires...for whatever reason you have not shared this information with us. Consequently, no one else can tell you what sort of filter would be "good enough".

– Elliot Alderson
Jan 22 at 23:16

|
show 3 more comments

Edit:

I just looked at the data sheet for the part. Go take a look at page 3, Input Impedance. Loading certainly will not be an issue.

answered Jan 21 at 1:49

Rudy

2616

$begingroup$
Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!
$endgroup$
– Henry
Jan 21 at 14:17

add a comment |

Edit:

I just looked at the data sheet for the part. Go take a look at page 3, Input Impedance. Loading certainly will not be an issue.

answered Jan 21 at 1:49

Rudy

2616

$begingroup$
Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!
$endgroup$
– Henry
Jan 21 at 14:17

add a comment |

Edit:

I just looked at the data sheet for the part. Go take a look at page 3, Input Impedance. Loading certainly will not be an issue.

answered Jan 21 at 1:49

Rudy

2616

Edit:

I just looked at the data sheet for the part. Go take a look at page 3, Input Impedance. Loading certainly will not be an issue.

answered Jan 21 at 1:49

Rudy

2616

answered Jan 21 at 1:49

Rudy

2616

answered Jan 21 at 1:49

Rudy

2616

answered Jan 21 at 1:49

Rudy

2616

$begingroup$
Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!
$endgroup$
– Henry
Jan 21 at 14:17

add a comment |

$begingroup$
Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!
$endgroup$
– Henry
Jan 21 at 14:17

Ok so you suggest I could increase the values of the resistors but in general there should not be any problems using this filter in my configuration? I'm a bit confused as the answers by Dmitry Grigoryev and Elliot Alderson indicate problems with the current filter configuration. Could you please make a comment on that? (Do you see the same problems as the two answers I named?). Thank you!

– Henry
Jan 21 at 14:17

add a comment |

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

$begingroup$
So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?
$endgroup$
– Henry
Jan 21 at 17:03

$begingroup$
Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.
$endgroup$
– Henry
Jan 22 at 22:41

$begingroup$
@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.
$endgroup$
– Dmitry Grigoryev
Jan 23 at 8:31

$begingroup$
I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!
$endgroup$
– Henry
Jan 23 at 21:18

1

$begingroup$
ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.
$endgroup$
– Dmitry Grigoryev
Jan 24 at 15:19

|
show 4 more comments

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

$begingroup$
So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?
$endgroup$
– Henry
Jan 21 at 17:03

$begingroup$
Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.
$endgroup$
– Henry
Jan 22 at 22:41

$begingroup$
@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.
$endgroup$
– Dmitry Grigoryev
Jan 23 at 8:31

$begingroup$
I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!
$endgroup$
– Henry
Jan 23 at 21:18

1

$begingroup$
ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.
$endgroup$
– Dmitry Grigoryev
Jan 24 at 15:19

|
show 4 more comments

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

answered Jan 21 at 8:16

Dmitry Grigoryev

18k22775

$begingroup$
So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?
$endgroup$
– Henry
Jan 21 at 17:03

$begingroup$
Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.
$endgroup$
– Henry
Jan 22 at 22:41

$begingroup$
@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.
$endgroup$
– Dmitry Grigoryev
Jan 23 at 8:31

$begingroup$
I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!
$endgroup$
– Henry
Jan 23 at 21:18

1

$begingroup$
ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.
$endgroup$
– Dmitry Grigoryev
Jan 24 at 15:19

|
show 4 more comments

$begingroup$
So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?
$endgroup$
– Henry
Jan 21 at 17:03

$begingroup$
Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.
$endgroup$
– Henry
Jan 22 at 22:41

$begingroup$
@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.
$endgroup$
– Dmitry Grigoryev
Jan 23 at 8:31

$begingroup$
I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!
$endgroup$
– Henry
Jan 23 at 21:18

1

$begingroup$
ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.
$endgroup$
– Dmitry Grigoryev
Jan 24 at 15:19

So the series resistance of my filter (in this case the resistance of the 3 cascaded resistors) must be at least 10kOhm? So the current drawn from the In-amp is limited and does not get too high? Would such a high resistance not heavily impact my signal?

– Henry
Jan 21 at 17:03

Could you please elaborate on this issue? What effect would it have on my circuit in case I use the proposed filter? Thank you.

– Henry
Jan 22 at 22:41

@Henry I'm talking about the resistance from amp output to ground, not to ADC input. Even if we consider only R1 and C1, the resistance is 200 + 100 (at 100 Hz) = 300 Ohm, which is way too low.

– Dmitry Grigoryev
Jan 23 at 8:31

I dont get the problem to be honest. I want the resistance to be low after the IN-Amp output (the ADC input has high input impedance) in the signal trace dont I? And I want to short AC to ground also. What would you change in the said configuration, could you name the values you would use? Thank you!

– Henry
Jan 23 at 21:18

ADC input is high impedance and poses no problem. The primary contributor to low resistance is your RC filter. Again: a 22µF capacitor has an equivalent resistance of 100 Ohm at 100Hz. If your signal has a significant AC component, you will overload the amplifier.

– Dmitry Grigoryev
Jan 24 at 15:19

|
show 4 more comments

The ADC input will look like a SHORT, for 5 or 10 nanoSeconds, at beginning of the Sample time. That "short" will disrupt any opamp directly connected to the ADC Vin or the ADC VREF.

To prevent this "disruption" (which shows up as ringing, and perhaps input-voltage-dependent quantization errors, we can place LARGE capacitors on the Vin and the VREF pins.

Assume the ADC has 10pF capacitors on its Vin and VREF pins, and assume these capacitors have had their charge consumed during the just-prior ADC operation.

As the ADC once again grabs some charge, there will be surge currents demanded from the external voltage sources(Vin and/or VREF).

To minimize the voltage upset, use LARGE external capacitors: 100X or 1,000X or 10,000X larger than the ADC sample (10pF) capacitors.

In the 3-cascaded_RC filter I gave you, that final capacitor is 10nF (10,000 pF) and should work well.

answered Jan 31 at 3:41

analogsystemsrf

15k2719

add a comment |

The ADC input will look like a SHORT, for 5 or 10 nanoSeconds, at beginning of the Sample time. That "short" will disrupt any opamp directly connected to the ADC Vin or the ADC VREF.

To prevent this "disruption" (which shows up as ringing, and perhaps input-voltage-dependent quantization errors, we can place LARGE capacitors on the Vin and the VREF pins.

Assume the ADC has 10pF capacitors on its Vin and VREF pins, and assume these capacitors have had their charge consumed during the just-prior ADC operation.

As the ADC once again grabs some charge, there will be surge currents demanded from the external voltage sources(Vin and/or VREF).

To minimize the voltage upset, use LARGE external capacitors: 100X or 1,000X or 10,000X larger than the ADC sample (10pF) capacitors.

In the 3-cascaded_RC filter I gave you, that final capacitor is 10nF (10,000 pF) and should work well.

answered Jan 31 at 3:41

analogsystemsrf

15k2719

add a comment |

The ADC input will look like a SHORT, for 5 or 10 nanoSeconds, at beginning of the Sample time. That "short" will disrupt any opamp directly connected to the ADC Vin or the ADC VREF.

To prevent this "disruption" (which shows up as ringing, and perhaps input-voltage-dependent quantization errors, we can place LARGE capacitors on the Vin and the VREF pins.

Assume the ADC has 10pF capacitors on its Vin and VREF pins, and assume these capacitors have had their charge consumed during the just-prior ADC operation.

As the ADC once again grabs some charge, there will be surge currents demanded from the external voltage sources(Vin and/or VREF).

To minimize the voltage upset, use LARGE external capacitors: 100X or 1,000X or 10,000X larger than the ADC sample (10pF) capacitors.

In the 3-cascaded_RC filter I gave you, that final capacitor is 10nF (10,000 pF) and should work well.

answered Jan 31 at 3:41

analogsystemsrf

15k2719

The ADC input will look like a SHORT, for 5 or 10 nanoSeconds, at beginning of the Sample time. That "short" will disrupt any opamp directly connected to the ADC Vin or the ADC VREF.

To prevent this "disruption" (which shows up as ringing, and perhaps input-voltage-dependent quantization errors, we can place LARGE capacitors on the Vin and the VREF pins.

Assume the ADC has 10pF capacitors on its Vin and VREF pins, and assume these capacitors have had their charge consumed during the just-prior ADC operation.

As the ADC once again grabs some charge, there will be surge currents demanded from the external voltage sources(Vin and/or VREF).

To minimize the voltage upset, use LARGE external capacitors: 100X or 1,000X or 10,000X larger than the ADC sample (10pF) capacitors.

In the 3-cascaded_RC filter I gave you, that final capacitor is 10nF (10,000 pF) and should work well.

answered Jan 31 at 3:41

analogsystemsrf

15k2719

answered Jan 31 at 3:41

analogsystemsrf

15k2719

answered Jan 31 at 3:41

analogsystemsrf

15k2719

answered Jan 31 at 3:41

analogsystemsrf

15k2719

add a comment |

I displayed the parameters on the schematic so you can lift them if you use LTspice.

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

$begingroup$
sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.
$endgroup$
– Henry
Jan 21 at 12:21

$begingroup$
Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?
$endgroup$
– Henry
Jan 22 at 22:44

add a comment |

I displayed the parameters on the schematic so you can lift them if you use LTspice.

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

$begingroup$
sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.
$endgroup$
– Henry
Jan 21 at 12:21

$begingroup$
Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?
$endgroup$
– Henry
Jan 22 at 22:44

add a comment |

I displayed the parameters on the schematic so you can lift them if you use LTspice.

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

I displayed the parameters on the schematic so you can lift them if you use LTspice.

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

edited Jan 23 at 11:08

answered Jan 21 at 3:09

Bizibill

answered Jan 21 at 3:09

Bizibill

answered Jan 21 at 3:09

Bizibill

$begingroup$
sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.
$endgroup$
– Henry
Jan 21 at 12:21

$begingroup$
Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?
$endgroup$
– Henry
Jan 22 at 22:44

add a comment |

$begingroup$
sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.
$endgroup$
– Henry
Jan 21 at 12:21

$begingroup$
Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?
$endgroup$
– Henry
Jan 22 at 22:44

sounds good, can you elaborate on this approach or link me to an example (maybe provide a small example circuit yourself with brief explanation) as I do not understand your approach well yet, thank you.

– Henry
Jan 21 at 12:21

Thank you for your input! Interesting, source would be nice so I can play around a bit. But you are using active components in the filters as well? Or do I misunderstand your approach here?

– Henry
Jan 22 at 22:44

add a comment |

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