Mixing
How can I replace the syntax “wait on a” in vhdl with equivalent syntax that won't initiate an infinite...
1
I am working on a single cycle processor using vhdl. I was trying to solve bugs in the code but eventually we were trapped in two situations in the instruction memory and data memory(in imem & dmem):
- there is a part in the code ( “wait on a”) that can’t be synthesized on quarus and also a problem with loops that make the code loop infinitely on quartus
- we tried to replace loops and (wait on a) with (process(a)) but also we have a problem that there can’t be a process inside another process.
How can I solve these bugs?
library IEEE;
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_arith.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is -- instruction memory
type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable i, index, result: integer;
--type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to 63 loop -- set all contents low
mem(i) := (others => '0');
end loop;
index := 0;
FILE_OPEN(mem_file, "memfile.dat", READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := character'pos(ch) - character'pos('a') + 10;
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else report "Formaterror on line " & integer'image(index)
severity error;
end if;
mem(index)(35-i*4 downto 32-i*4) :=conv_std_logic_vector(result,4);
end loop;
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(conv_integer(unsigned(a(7 downto 2))));
wait on a;
end loop;
end process;
end;
vhdl altera quartus
edited Jan 2 at 21:39
Paebbels
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
add a comment |
1
I am working on a single cycle processor using vhdl. I was trying to solve bugs in the code but eventually we were trapped in two situations in the instruction memory and data memory(in imem & dmem):
- there is a part in the code ( “wait on a”) that can’t be synthesized on quarus and also a problem with loops that make the code loop infinitely on quartus
- we tried to replace loops and (wait on a) with (process(a)) but also we have a problem that there can’t be a process inside another process.
How can I solve these bugs?
library IEEE;
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_arith.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is -- instruction memory
type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable i, index, result: integer;
--type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to 63 loop -- set all contents low
mem(i) := (others => '0');
end loop;
index := 0;
FILE_OPEN(mem_file, "memfile.dat", READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := character'pos(ch) - character'pos('a') + 10;
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else report "Formaterror on line " & integer'image(index)
severity error;
end if;
mem(index)(35-i*4 downto 32-i*4) :=conv_std_logic_vector(result,4);
end loop;
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(conv_integer(unsigned(a(7 downto 2))));
wait on a;
end loop;
end process;
end;
vhdl altera quartus
edited Jan 2 at 21:39
Paebbels
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole packagetextiofor file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL libraryaltera_mfcalledaltsyncramto represent a RAM or ROM. The PoC-Library has an implementation here.
– Paebbels
Jan 2 at 21:46
add a comment |
1
1
1
I am working on a single cycle processor using vhdl. I was trying to solve bugs in the code but eventually we were trapped in two situations in the instruction memory and data memory(in imem & dmem):
- there is a part in the code ( “wait on a”) that can’t be synthesized on quarus and also a problem with loops that make the code loop infinitely on quartus
- we tried to replace loops and (wait on a) with (process(a)) but also we have a problem that there can’t be a process inside another process.
How can I solve these bugs?
library IEEE;
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_arith.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is -- instruction memory
type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable i, index, result: integer;
--type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to 63 loop -- set all contents low
mem(i) := (others => '0');
end loop;
index := 0;
FILE_OPEN(mem_file, "memfile.dat", READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := character'pos(ch) - character'pos('a') + 10;
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else report "Formaterror on line " & integer'image(index)
severity error;
end if;
mem(index)(35-i*4 downto 32-i*4) :=conv_std_logic_vector(result,4);
end loop;
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(conv_integer(unsigned(a(7 downto 2))));
wait on a;
end loop;
end process;
end;
vhdl altera quartus
edited Jan 2 at 21:39
Paebbels
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
I am working on a single cycle processor using vhdl. I was trying to solve bugs in the code but eventually we were trapped in two situations in the instruction memory and data memory(in imem & dmem):
- there is a part in the code ( “wait on a”) that can’t be synthesized on quarus and also a problem with loops that make the code loop infinitely on quartus
- we tried to replace loops and (wait on a) with (process(a)) but also we have a problem that there can’t be a process inside another process.
How can I solve these bugs?
library IEEE;
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_arith.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is -- instruction memory
type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable i, index, result: integer;
--type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to 63 loop -- set all contents low
mem(i) := (others => '0');
end loop;
index := 0;
FILE_OPEN(mem_file, "memfile.dat", READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := character'pos(ch) - character'pos('a') + 10;
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else report "Formaterror on line " & integer'image(index)
severity error;
end if;
mem(index)(35-i*4 downto 32-i*4) :=conv_std_logic_vector(result,4);
end loop;
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(conv_integer(unsigned(a(7 downto 2))));
wait on a;
end loop;
end process;
end;
vhdl altera quartus
vhdl altera quartus
edited Jan 2 at 21:39
Paebbels
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
edited Jan 2 at 21:39
Paebbels
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
edited Jan 2 at 21:39
Paebbels
7,68383580
edited Jan 2 at 21:39
Paebbels
7,68383580
edited Jan 2 at 21:39
Paebbels
7,68383580
7,68383580
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
asked Jan 2 at 16:36
Ahmed AbdelkarimAhmed Abdelkarim
61
61
As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole packagetextiofor file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL libraryaltera_mfcalledaltsyncramto represent a RAM or ROM. The PoC-Library has an implementation here.
– Paebbels
Jan 2 at 21:46
add a comment |
As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole packagetextiofor file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL libraryaltera_mfcalledaltsyncramto represent a RAM or ROM. The PoC-Library has an implementation here.
– Paebbels
Jan 2 at 21:46
As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package
textio for file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.– Paebbels
Jan 2 at 21:46
As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package
textio for file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.– Paebbels
Jan 2 at 21:46
add a comment |
1 Answer
1
active
oldest
votes
4
As reported by @Tricky, I overlooked that you're using quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package textio for file I/O is not supported / ignored. You need to use the Altera Mega Function primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.
altsyncram example for a single-port RAM:
library altera_mf;
use altera_mf.all;
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => getAlteraDeviceName(DEVICE),
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/altera/ocram_sp_altera.vhdl?ts=2
Original answer:
You need to put your RAM initializing code into a function, which is returning the initial values for your RAM. In the function, you read the external file and convert each line to a memory value.
Here are some snippets to get you onto the right way:
architecture a of e is
type ram_type is array(natural range <>) of std_logic_vector(31 downto 0);
function initialize(
constant file_name : string;
constant size : positive
) return ram_type is
file mem_file : text;
variable result : ram_type(0 to size - 1);
begin
file_open(mem_file, file_name, READ_MODE);
while not endfile(mem_file) loop
-- ... read and convert content
end loop;
file_close(mem_file);
return result;
end function;
signal mem : ram_type := initialize("memfile.dat", 64);
begin
process(a)
begin
rd <= mem(to_integer(unsigned(a(7 downto 2))));
end process;
More hints:
- Normally reading an instruction memory (BlockRAM) is a clocked process. Currently you are reading asynchronously on every address change.
- A
wait onstatement is equivalent to a process with a sensitivity list. - You should close opened files.
- Don't use package
STD_LOGIC_arith, usenumeric_stdinstead.
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added thealtera_mf.altsyncramexample, which can read memory initialization files (MIF) files.
– Paebbels
Jan 2 at 21:52
add a comment |
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1 Answer
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1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
4
As reported by @Tricky, I overlooked that you're using quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package textio for file I/O is not supported / ignored. You need to use the Altera Mega Function primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.
altsyncram example for a single-port RAM:
library altera_mf;
use altera_mf.all;
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => getAlteraDeviceName(DEVICE),
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/altera/ocram_sp_altera.vhdl?ts=2
Original answer:
You need to put your RAM initializing code into a function, which is returning the initial values for your RAM. In the function, you read the external file and convert each line to a memory value.
Here are some snippets to get you onto the right way:
architecture a of e is
type ram_type is array(natural range <>) of std_logic_vector(31 downto 0);
function initialize(
constant file_name : string;
constant size : positive
) return ram_type is
file mem_file : text;
variable result : ram_type(0 to size - 1);
begin
file_open(mem_file, file_name, READ_MODE);
while not endfile(mem_file) loop
-- ... read and convert content
end loop;
file_close(mem_file);
return result;
end function;
signal mem : ram_type := initialize("memfile.dat", 64);
begin
process(a)
begin
rd <= mem(to_integer(unsigned(a(7 downto 2))));
end process;
More hints:
- Normally reading an instruction memory (BlockRAM) is a clocked process. Currently you are reading asynchronously on every address change.
- A
wait onstatement is equivalent to a process with a sensitivity list. - You should close opened files.
- Don't use package
STD_LOGIC_arith, usenumeric_stdinstead.
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added thealtera_mf.altsyncramexample, which can read memory initialization files (MIF) files.
– Paebbels
Jan 2 at 21:52
add a comment |
4
As reported by @Tricky, I overlooked that you're using quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package textio for file I/O is not supported / ignored. You need to use the Altera Mega Function primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.
altsyncram example for a single-port RAM:
library altera_mf;
use altera_mf.all;
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => getAlteraDeviceName(DEVICE),
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/altera/ocram_sp_altera.vhdl?ts=2
Original answer:
You need to put your RAM initializing code into a function, which is returning the initial values for your RAM. In the function, you read the external file and convert each line to a memory value.
Here are some snippets to get you onto the right way:
architecture a of e is
type ram_type is array(natural range <>) of std_logic_vector(31 downto 0);
function initialize(
constant file_name : string;
constant size : positive
) return ram_type is
file mem_file : text;
variable result : ram_type(0 to size - 1);
begin
file_open(mem_file, file_name, READ_MODE);
while not endfile(mem_file) loop
-- ... read and convert content
end loop;
file_close(mem_file);
return result;
end function;
signal mem : ram_type := initialize("memfile.dat", 64);
begin
process(a)
begin
rd <= mem(to_integer(unsigned(a(7 downto 2))));
end process;
More hints:
- Normally reading an instruction memory (BlockRAM) is a clocked process. Currently you are reading asynchronously on every address change.
- A
wait onstatement is equivalent to a process with a sensitivity list. - You should close opened files.
- Don't use package
STD_LOGIC_arith, usenumeric_stdinstead.
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added thealtera_mf.altsyncramexample, which can read memory initialization files (MIF) files.
– Paebbels
Jan 2 at 21:52
add a comment |
4
4
4
As reported by @Tricky, I overlooked that you're using quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package textio for file I/O is not supported / ignored. You need to use the Altera Mega Function primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.
altsyncram example for a single-port RAM:
library altera_mf;
use altera_mf.all;
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => getAlteraDeviceName(DEVICE),
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/altera/ocram_sp_altera.vhdl?ts=2
Original answer:
You need to put your RAM initializing code into a function, which is returning the initial values for your RAM. In the function, you read the external file and convert each line to a memory value.
Here are some snippets to get you onto the right way:
architecture a of e is
type ram_type is array(natural range <>) of std_logic_vector(31 downto 0);
function initialize(
constant file_name : string;
constant size : positive
) return ram_type is
file mem_file : text;
variable result : ram_type(0 to size - 1);
begin
file_open(mem_file, file_name, READ_MODE);
while not endfile(mem_file) loop
-- ... read and convert content
end loop;
file_close(mem_file);
return result;
end function;
signal mem : ram_type := initialize("memfile.dat", 64);
begin
process(a)
begin
rd <= mem(to_integer(unsigned(a(7 downto 2))));
end process;
More hints:
- Normally reading an instruction memory (BlockRAM) is a clocked process. Currently you are reading asynchronously on every address change.
- A
wait onstatement is equivalent to a process with a sensitivity list. - You should close opened files.
- Don't use package
STD_LOGIC_arith, usenumeric_stdinstead.
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
As reported by @Tricky, I overlooked that you're using quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package textio for file I/O is not supported / ignored. You need to use the Altera Mega Function primitives from VHDL library altera_mf called altsyncram to represent a RAM or ROM. The PoC-Library has an implementation here.
altsyncram example for a single-port RAM:
library altera_mf;
use altera_mf.all;
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => getAlteraDeviceName(DEVICE),
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
Source: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/altera/ocram_sp_altera.vhdl?ts=2
Original answer:
You need to put your RAM initializing code into a function, which is returning the initial values for your RAM. In the function, you read the external file and convert each line to a memory value.
Here are some snippets to get you onto the right way:
architecture a of e is
type ram_type is array(natural range <>) of std_logic_vector(31 downto 0);
function initialize(
constant file_name : string;
constant size : positive
) return ram_type is
file mem_file : text;
variable result : ram_type(0 to size - 1);
begin
file_open(mem_file, file_name, READ_MODE);
while not endfile(mem_file) loop
-- ... read and convert content
end loop;
file_close(mem_file);
return result;
end function;
signal mem : ram_type := initialize("memfile.dat", 64);
begin
process(a)
begin
rd <= mem(to_integer(unsigned(a(7 downto 2))));
end process;
More hints:
- Normally reading an instruction memory (BlockRAM) is a clocked process. Currently you are reading asynchronously on every address change.
- A
wait onstatement is equivalent to a process with a sensitivity list. - You should close opened files.
- Don't use package
STD_LOGIC_arith, usenumeric_stdinstead.
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
edited Jan 2 at 21:52
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
answered Jan 2 at 17:10
PaebbelsPaebbels
7,68383580
7,68383580
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added thealtera_mf.altsyncramexample, which can read memory initialization files (MIF) files.
– Paebbels
Jan 2 at 21:52
add a comment |
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added thealtera_mf.altsyncramexample, which can read memory initialization files (MIF) files.
– Paebbels
Jan 2 at 21:52
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
There is an issue here - the OP says they are using Quartus, and while the code is valid, Quartus does not support textio for memory initialisation during synthesis. @AhmedAbdelkarim will need to use a .mif file for this (but the above code is required for simulation)
– Tricky
Jan 2 at 18:27
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
@Tricky You are right, I overlooked the "Quartus" hint. Is the new Quartus from Intel still as restrictive on this silly feature request? On one side they support generic types in entities (VHDL-2008 feature normally only supported in simulators) and on the user side they refuse to support textio ...
– Paebbels
Jan 2 at 21:42
I added the
altera_mf.altsyncram example, which can read memory initialization files (MIF) files.– Paebbels
Jan 2 at 21:52
I added the
altera_mf.altsyncram example, which can read memory initialization files (MIF) files.– Paebbels
Jan 2 at 21:52
add a comment |
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As reported by @Tricky, I overlooked that you're using Quartus. As far was we both know, Quartus does not support reading files in initializer functions. The whole package
textiofor file I/O is not supported / ignored. You need to use the Altera MegaFunction primitives from VHDL libraryaltera_mfcalledaltsyncramto represent a RAM or ROM. The PoC-Library has an implementation here.– Paebbels
Jan 2 at 21:46