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How to import getVerilog() function from the bootcamp examples?
I am not sure I understand how to use the getVerilog function from:
https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
I did import chisel3._ but that does not seem to be enough.
chisel
asked Nov 21 '18 at 14:20
cayluscaylus
12816
add a comment |
I am not sure I understand how to use the getVerilog function from:
https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
I did import chisel3._ but that does not seem to be enough.
chisel
asked Nov 21 '18 at 14:20
cayluscaylus
12816
add a comment |
I am not sure I understand how to use the getVerilog function from:
https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
I did import chisel3._ but that does not seem to be enough.
chisel
asked Nov 21 '18 at 14:20
cayluscaylus
12816
I am not sure I understand how to use the getVerilog function from:
https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
I did import chisel3._ but that does not seem to be enough.
chisel
chisel
asked Nov 21 '18 at 14:20
cayluscaylus
12816
asked Nov 21 '18 at 14:20
cayluscaylus
12816
asked Nov 21 '18 at 14:20
cayluscaylus
12816
asked Nov 21 '18 at 14:20
cayluscaylus
12816
asked Nov 21 '18 at 14:20
cayluscaylus
12816
12816
add a comment |
add a comment |
1 Answer
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The getVerilog method is defined only in the Bootcamp. There's an equivalent method via Chisel's Driver.emitVerilog:
import chisel3._
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
println(Driver.emitVerilog(new Foo))
For additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., I forgot that emitVerilog exists and only realized it when looking at the Driver API.
If you are looking for more control over the FIRRTL or Verilog generation process, you'll want to use the Driver.execute(args: Array[String], dut: () => RawModule) API. That lets you pass arguments to Chisel's Driver whereas emitVerilog is a one-shot "just get me some Verilog."
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
add a comment |
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1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
The getVerilog method is defined only in the Bootcamp. There's an equivalent method via Chisel's Driver.emitVerilog:
import chisel3._
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
println(Driver.emitVerilog(new Foo))
For additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., I forgot that emitVerilog exists and only realized it when looking at the Driver API.
If you are looking for more control over the FIRRTL or Verilog generation process, you'll want to use the Driver.execute(args: Array[String], dut: () => RawModule) API. That lets you pass arguments to Chisel's Driver whereas emitVerilog is a one-shot "just get me some Verilog."
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
add a comment |
The getVerilog method is defined only in the Bootcamp. There's an equivalent method via Chisel's Driver.emitVerilog:
import chisel3._
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
println(Driver.emitVerilog(new Foo))
For additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., I forgot that emitVerilog exists and only realized it when looking at the Driver API.
If you are looking for more control over the FIRRTL or Verilog generation process, you'll want to use the Driver.execute(args: Array[String], dut: () => RawModule) API. That lets you pass arguments to Chisel's Driver whereas emitVerilog is a one-shot "just get me some Verilog."
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
add a comment |
The getVerilog method is defined only in the Bootcamp. There's an equivalent method via Chisel's Driver.emitVerilog:
import chisel3._
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
println(Driver.emitVerilog(new Foo))
For additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., I forgot that emitVerilog exists and only realized it when looking at the Driver API.
If you are looking for more control over the FIRRTL or Verilog generation process, you'll want to use the Driver.execute(args: Array[String], dut: () => RawModule) API. That lets you pass arguments to Chisel's Driver whereas emitVerilog is a one-shot "just get me some Verilog."
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
The getVerilog method is defined only in the Bootcamp. There's an equivalent method via Chisel's Driver.emitVerilog:
import chisel3._
class Foo extends Module {
val io = IO(new Bundle {})
printf("I'm a foo")
}
println(Driver.emitVerilog(new Foo))
For additional reference, the specific implementation of getVerilog in the Chisel Bootcamp is here. This looks almost identical to what Driver.emitVerilog is doing here. There was a similar, but slightly different question about generating Verilog that was brought up in a different SO question.
Usually if you're wondering if some API exists, it can be useful to search through the Chisel3 API reference. E.g., I forgot that emitVerilog exists and only realized it when looking at the Driver API.
If you are looking for more control over the FIRRTL or Verilog generation process, you'll want to use the Driver.execute(args: Array[String], dut: () => RawModule) API. That lets you pass arguments to Chisel's Driver whereas emitVerilog is a one-shot "just get me some Verilog."
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
edited Nov 21 '18 at 15:39
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
answered Nov 21 '18 at 15:22
seldridgeseldridge
64559
64559
add a comment |
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