Mixing
Problem with CLK in implementing counter in VHDL
0
I am trying to implement counter which gives as output values from one to six, which I want to later put on 7 segment display on fpga. The problem is with CLK, process doesn't see value of CLK changing and simulation gives as output always set of values "1001111".
library ieee;
use ieee.std_logic_1164.all;
entity projekt is
generic ( half_period : time := 10ms);
port(Q : out std_logic_vector(6 downto 0));
end projekt;
architecture a1 of projekt is
signal CLK : std_logic := '0';
begin
CLK <= not CLK after half_period;
process(CLK)
variable tmpQ : integer range 0 to 7 := 1;
begin
if ( CLK = '1' and CLK'event ) then
tmpQ := tmpQ + 1;
if tmpQ = 7 then
tmpQ := 1;
end if;
end if;
case tmpQ is
when 1 => Q <= "1001111";
when 2 => Q <= "0010010";
when 3 => Q <= "0000110";
when 4 => Q <= "1001100";
when 5 => Q <= "0100100";
when 6 => Q <= "0100000";
when others => Q <= "1111111";
end case;
end process;
end a1;
Is it CLK not changing or program never enters if statement?
vhdl fpga
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
add a comment |
0
I am trying to implement counter which gives as output values from one to six, which I want to later put on 7 segment display on fpga. The problem is with CLK, process doesn't see value of CLK changing and simulation gives as output always set of values "1001111".
library ieee;
use ieee.std_logic_1164.all;
entity projekt is
generic ( half_period : time := 10ms);
port(Q : out std_logic_vector(6 downto 0));
end projekt;
architecture a1 of projekt is
signal CLK : std_logic := '0';
begin
CLK <= not CLK after half_period;
process(CLK)
variable tmpQ : integer range 0 to 7 := 1;
begin
if ( CLK = '1' and CLK'event ) then
tmpQ := tmpQ + 1;
if tmpQ = 7 then
tmpQ := 1;
end if;
end if;
case tmpQ is
when 1 => Q <= "1001111";
when 2 => Q <= "0010010";
when 3 => Q <= "0000110";
when 4 => Q <= "1001100";
when 5 => Q <= "0100100";
when 6 => Q <= "0100000";
when others => Q <= "1111111";
end case;
end process;
end a1;
Is it CLK not changing or program never enters if statement?
vhdl fpga
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
1
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08
add a comment |
0
0
0
I am trying to implement counter which gives as output values from one to six, which I want to later put on 7 segment display on fpga. The problem is with CLK, process doesn't see value of CLK changing and simulation gives as output always set of values "1001111".
library ieee;
use ieee.std_logic_1164.all;
entity projekt is
generic ( half_period : time := 10ms);
port(Q : out std_logic_vector(6 downto 0));
end projekt;
architecture a1 of projekt is
signal CLK : std_logic := '0';
begin
CLK <= not CLK after half_period;
process(CLK)
variable tmpQ : integer range 0 to 7 := 1;
begin
if ( CLK = '1' and CLK'event ) then
tmpQ := tmpQ + 1;
if tmpQ = 7 then
tmpQ := 1;
end if;
end if;
case tmpQ is
when 1 => Q <= "1001111";
when 2 => Q <= "0010010";
when 3 => Q <= "0000110";
when 4 => Q <= "1001100";
when 5 => Q <= "0100100";
when 6 => Q <= "0100000";
when others => Q <= "1111111";
end case;
end process;
end a1;
Is it CLK not changing or program never enters if statement?
vhdl fpga
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
I am trying to implement counter which gives as output values from one to six, which I want to later put on 7 segment display on fpga. The problem is with CLK, process doesn't see value of CLK changing and simulation gives as output always set of values "1001111".
library ieee;
use ieee.std_logic_1164.all;
entity projekt is
generic ( half_period : time := 10ms);
port(Q : out std_logic_vector(6 downto 0));
end projekt;
architecture a1 of projekt is
signal CLK : std_logic := '0';
begin
CLK <= not CLK after half_period;
process(CLK)
variable tmpQ : integer range 0 to 7 := 1;
begin
if ( CLK = '1' and CLK'event ) then
tmpQ := tmpQ + 1;
if tmpQ = 7 then
tmpQ := 1;
end if;
end if;
case tmpQ is
when 1 => Q <= "1001111";
when 2 => Q <= "0010010";
when 3 => Q <= "0000110";
when 4 => Q <= "1001100";
when 5 => Q <= "0100100";
when 6 => Q <= "0100000";
when others => Q <= "1111111";
end case;
end process;
end a1;
Is it CLK not changing or program never enters if statement?
vhdl fpga
vhdl fpga
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
edited Nov 22 '18 at 10:58
Jerzy Wenta
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
asked Nov 22 '18 at 10:15
Jerzy WentaJerzy Wenta
11
11
What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
1
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08
add a comment |
What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
1
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08
What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
1
1
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08
add a comment |
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What are you simulating? RTL sim or netlist simulation? you cannot synthesise "after" statements, so if you're simulation is a netlist clock is probably stuck at '0'. Your code is only valid for simulation and will not work on an FPGA.
– Tricky
Nov 22 '18 at 11:34
@Tricky I am doing simple waveform simulation using software "Quartus 2". Can you explain in more details what do you mean by "synthesizing "after" "?
– Jerzy Wenta
Nov 22 '18 at 12:11
1
Quartus simulator does a netlist simulation. So your clock is stuck at 0. You will need to perform an RTL simulation on something like Modelsim to see your clock actually clocking. But the point remains, this code will not work on real hardware (as demonstrated in the Q2 simulation).
– Tricky
Nov 22 '18 at 14:08