VHDL : how to use rem and mod command in VHDL ? (syntax problem)

hello I want to take the binary number of 23. and in binary form it is : 010111

so if for example 23 mod 10 i will get 3 . how to do this comand in VHDL ? this is what I wrote so far :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY rem_command IS

  GENERIC (display_resolution : INTEGER :=23;   -- counter to get to the loest ferquncy 

  display_counter: INTEGER :=8);        -- counter to get to 97KHz ferquincy 



PORT (

    CLK_IN :IN STD_LOGIC;

    PWM_LIMIT :IN STD_LOGIC_VECTOR(display_counter downto 0);

    COUNTER_VECTOR :IN  STD_LOGIC_VECTOR(display_counter downto 0);

    number_out: OUT  STD_LOGIC 

    );

END rem_command;



ARCHITECTURE testing_reminder_command  OF  rem_command  I

    signal number : std_logic_vector(5 downto 0):="010111"; -- this is 23 in binary form 

BEGIN

        process(COUNTER_VECTOR,PWM_LIMIT,CLK_IN,number)

        BEGIN

                number <= 10 MOD number;                                                

        end process;



    number_out<=number;



END testing_reminder_command ;

the error that I get is :

Error (10327): VHDL error at rem_command.vhd(48): can't determine
definition of operator ""mod"" -- found 0 possible definitions

maybe I need to add library ?

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

1

You need to read my answer here .

– Matthew Taylor
Nov 20 '18 at 10:35

I am sorry but I don't understand how can it help my problem

– Tomer Polski
Nov 20 '18 at 10:48

Your problem is exactly the same: the mod and rem operators are not defined for std_logic_vector. You need to use a different type, for which they are defined, for example unsigned. Basically, never use the std_logic_vector type for doing maths. It is not intended for that. If you're new to the unsigned type and type conversions, then have a look at these examples.

– Matthew Taylor
Nov 20 '18 at 10:58

You'll find with number declared as type unsigned the assignment to number_out fails. number_out is type std_logic (and should be either std_logic_vector or unsigned with a matching element for each element of number, checked during signal update in simulation). If number_out is std_logic_vector (5 downto 0) then number must be be converted - number_out <= std_logic_vector(number); Type unsigned and std_logic_vector are closely related allowing type conversion, both having the same element base type (std_ulogic) and both single dimensional array types. THEN the code will analyze (compile).

– user1155120
Nov 20 '18 at 19:21

NOW comes a nasty part. number <= 10 mod number; with number in the process sensitivity list causes recursion, where eventually you'll divide by 0 during simulation, "DIV, MOD, or REM by zero" an error. The proper thing would be to merge the assignment of number_out - number_out <= std_logic_vector( 10 mod number); presumably in the process. These two comments presume using package numeric_std.

– user1155120
Nov 20 '18 at 19:32

add a comment |

hello I want to take the binary number of 23. and in binary form it is : 010111

so if for example 23 mod 10 i will get 3 . how to do this comand in VHDL ? this is what I wrote so far :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY rem_command IS

  GENERIC (display_resolution : INTEGER :=23;   -- counter to get to the loest ferquncy 

  display_counter: INTEGER :=8);        -- counter to get to 97KHz ferquincy 



PORT (

    CLK_IN :IN STD_LOGIC;

    PWM_LIMIT :IN STD_LOGIC_VECTOR(display_counter downto 0);

    COUNTER_VECTOR :IN  STD_LOGIC_VECTOR(display_counter downto 0);

    number_out: OUT  STD_LOGIC 

    );

END rem_command;



ARCHITECTURE testing_reminder_command  OF  rem_command  I

    signal number : std_logic_vector(5 downto 0):="010111"; -- this is 23 in binary form 

BEGIN

        process(COUNTER_VECTOR,PWM_LIMIT,CLK_IN,number)

        BEGIN

                number <= 10 MOD number;                                                

        end process;



    number_out<=number;



END testing_reminder_command ;

the error that I get is :

Error (10327): VHDL error at rem_command.vhd(48): can't determine
definition of operator ""mod"" -- found 0 possible definitions

maybe I need to add library ?

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

1

You need to read my answer here .

– Matthew Taylor
Nov 20 '18 at 10:35

I am sorry but I don't understand how can it help my problem

– Tomer Polski
Nov 20 '18 at 10:48

Your problem is exactly the same: the mod and rem operators are not defined for std_logic_vector. You need to use a different type, for which they are defined, for example unsigned. Basically, never use the std_logic_vector type for doing maths. It is not intended for that. If you're new to the unsigned type and type conversions, then have a look at these examples.

– Matthew Taylor
Nov 20 '18 at 10:58

You'll find with number declared as type unsigned the assignment to number_out fails. number_out is type std_logic (and should be either std_logic_vector or unsigned with a matching element for each element of number, checked during signal update in simulation). If number_out is std_logic_vector (5 downto 0) then number must be be converted - number_out <= std_logic_vector(number); Type unsigned and std_logic_vector are closely related allowing type conversion, both having the same element base type (std_ulogic) and both single dimensional array types. THEN the code will analyze (compile).

– user1155120
Nov 20 '18 at 19:21

NOW comes a nasty part. number <= 10 mod number; with number in the process sensitivity list causes recursion, where eventually you'll divide by 0 during simulation, "DIV, MOD, or REM by zero" an error. The proper thing would be to merge the assignment of number_out - number_out <= std_logic_vector( 10 mod number); presumably in the process. These two comments presume using package numeric_std.

– user1155120
Nov 20 '18 at 19:32

add a comment |

hello I want to take the binary number of 23. and in binary form it is : 010111

so if for example 23 mod 10 i will get 3 . how to do this comand in VHDL ? this is what I wrote so far :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY rem_command IS

  GENERIC (display_resolution : INTEGER :=23;   -- counter to get to the loest ferquncy 

  display_counter: INTEGER :=8);        -- counter to get to 97KHz ferquincy 



PORT (

    CLK_IN :IN STD_LOGIC;

    PWM_LIMIT :IN STD_LOGIC_VECTOR(display_counter downto 0);

    COUNTER_VECTOR :IN  STD_LOGIC_VECTOR(display_counter downto 0);

    number_out: OUT  STD_LOGIC 

    );

END rem_command;



ARCHITECTURE testing_reminder_command  OF  rem_command  I

    signal number : std_logic_vector(5 downto 0):="010111"; -- this is 23 in binary form 

BEGIN

        process(COUNTER_VECTOR,PWM_LIMIT,CLK_IN,number)

        BEGIN

                number <= 10 MOD number;                                                

        end process;



    number_out<=number;



END testing_reminder_command ;

the error that I get is :

Error (10327): VHDL error at rem_command.vhd(48): can't determine
definition of operator ""mod"" -- found 0 possible definitions

maybe I need to add library ?

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

hello I want to take the binary number of 23. and in binary form it is : 010111

so if for example 23 mod 10 i will get 3 . how to do this comand in VHDL ? this is what I wrote so far :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



ENTITY rem_command IS

  GENERIC (display_resolution : INTEGER :=23;   -- counter to get to the loest ferquncy 

  display_counter: INTEGER :=8);        -- counter to get to 97KHz ferquincy 



PORT (

    CLK_IN :IN STD_LOGIC;

    PWM_LIMIT :IN STD_LOGIC_VECTOR(display_counter downto 0);

    COUNTER_VECTOR :IN  STD_LOGIC_VECTOR(display_counter downto 0);

    number_out: OUT  STD_LOGIC 

    );

END rem_command;



ARCHITECTURE testing_reminder_command  OF  rem_command  I

    signal number : std_logic_vector(5 downto 0):="010111"; -- this is 23 in binary form 

BEGIN

        process(COUNTER_VECTOR,PWM_LIMIT,CLK_IN,number)

        BEGIN

                number <= 10 MOD number;                                                

        end process;



    number_out<=number;



END testing_reminder_command ;

the error that I get is :

Error (10327): VHDL error at rem_command.vhd(48): can't determine
definition of operator ""mod"" -- found 0 possible definitions

maybe I need to add library ?

syntax vhdl

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

edited Nov 20 '18 at 10:37

Matthew Taylor

7,1612731

asked Nov 20 '18 at 10:32

Tomer Polski

asked Nov 20 '18 at 10:32

Tomer Polski

asked Nov 20 '18 at 10:32

Tomer Polski

1

You need to read my answer here .

– Matthew Taylor
Nov 20 '18 at 10:35

I am sorry but I don't understand how can it help my problem

– Tomer Polski
Nov 20 '18 at 10:48

Your problem is exactly the same: the mod and rem operators are not defined for std_logic_vector. You need to use a different type, for which they are defined, for example unsigned. Basically, never use the std_logic_vector type for doing maths. It is not intended for that. If you're new to the unsigned type and type conversions, then have a look at these examples.

– Matthew Taylor
Nov 20 '18 at 10:58

You'll find with number declared as type unsigned the assignment to number_out fails. number_out is type std_logic (and should be either std_logic_vector or unsigned with a matching element for each element of number, checked during signal update in simulation). If number_out is std_logic_vector (5 downto 0) then number must be be converted - number_out <= std_logic_vector(number); Type unsigned and std_logic_vector are closely related allowing type conversion, both having the same element base type (std_ulogic) and both single dimensional array types. THEN the code will analyze (compile).

– user1155120
Nov 20 '18 at 19:21

NOW comes a nasty part. number <= 10 mod number; with number in the process sensitivity list causes recursion, where eventually you'll divide by 0 during simulation, "DIV, MOD, or REM by zero" an error. The proper thing would be to merge the assignment of number_out - number_out <= std_logic_vector( 10 mod number); presumably in the process. These two comments presume using package numeric_std.

– user1155120
Nov 20 '18 at 19:32

add a comment |

1

You need to read my answer here .

– Matthew Taylor
Nov 20 '18 at 10:35

I am sorry but I don't understand how can it help my problem

– Tomer Polski
Nov 20 '18 at 10:48

Your problem is exactly the same: the mod and rem operators are not defined for std_logic_vector. You need to use a different type, for which they are defined, for example unsigned. Basically, never use the std_logic_vector type for doing maths. It is not intended for that. If you're new to the unsigned type and type conversions, then have a look at these examples.

– Matthew Taylor
Nov 20 '18 at 10:58

You'll find with number declared as type unsigned the assignment to number_out fails. number_out is type std_logic (and should be either std_logic_vector or unsigned with a matching element for each element of number, checked during signal update in simulation). If number_out is std_logic_vector (5 downto 0) then number must be be converted - number_out <= std_logic_vector(number); Type unsigned and std_logic_vector are closely related allowing type conversion, both having the same element base type (std_ulogic) and both single dimensional array types. THEN the code will analyze (compile).

– user1155120
Nov 20 '18 at 19:21

NOW comes a nasty part. number <= 10 mod number; with number in the process sensitivity list causes recursion, where eventually you'll divide by 0 during simulation, "DIV, MOD, or REM by zero" an error. The proper thing would be to merge the assignment of number_out - number_out <= std_logic_vector( 10 mod number); presumably in the process. These two comments presume using package numeric_std.

– user1155120
Nov 20 '18 at 19:32

You need to read my answer here .

– Matthew Taylor
Nov 20 '18 at 10:35

I am sorry but I don't understand how can it help my problem

– Tomer Polski
Nov 20 '18 at 10:48

Your problem is exactly the same: the mod and rem operators are not defined for std_logic_vector. You need to use a different type, for which they are defined, for example unsigned. Basically, never use the std_logic_vector type for doing maths. It is not intended for that. If you're new to the unsigned type and type conversions, then have a look at these examples.

– Matthew Taylor
Nov 20 '18 at 10:58

You'll find with number declared as type unsigned the assignment to number_out fails. number_out is type std_logic (and should be either std_logic_vector or unsigned with a matching element for each element of number, checked during signal update in simulation). If number_out is std_logic_vector (5 downto 0) then number must be be converted - number_out <= std_logic_vector(number); Type unsigned and std_logic_vector are closely related allowing type conversion, both having the same element base type (std_ulogic) and both single dimensional array types. THEN the code will analyze (compile).

– user1155120
Nov 20 '18 at 19:21

NOW comes a nasty part. number <= 10 mod number; with number in the process sensitivity list causes recursion, where eventually you'll divide by 0 during simulation, "DIV, MOD, or REM by zero" an error. The proper thing would be to merge the assignment of number_out - number_out <= std_logic_vector( 10 mod number); presumably in the process. These two comments presume using package numeric_std.

– user1155120
Nov 20 '18 at 19:32

add a comment |

1 Answer
1

active

oldest

votes

If you definitely wanted to use the "mod" and "rem" operators:

They are not defined in any of the packages that you are using.

FIX: use ieee.numeric_std.all package

mod and rem don't operate on std_logic_vector. So, you need to implement type conversions on your std_logic_vector signals

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

1

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

add a comment |

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1 Answer
1

active

oldest

votes

1 Answer
1

active

oldest

votes

If you definitely wanted to use the "mod" and "rem" operators:

They are not defined in any of the packages that you are using.

FIX: use ieee.numeric_std.all package

mod and rem don't operate on std_logic_vector. So, you need to implement type conversions on your std_logic_vector signals

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

1

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

add a comment |

If you definitely wanted to use the "mod" and "rem" operators:

They are not defined in any of the packages that you are using.

FIX: use ieee.numeric_std.all package

mod and rem don't operate on std_logic_vector. So, you need to implement type conversions on your std_logic_vector signals

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

1

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

add a comment |

If you definitely wanted to use the "mod" and "rem" operators:

They are not defined in any of the packages that you are using.

FIX: use ieee.numeric_std.all package

mod and rem don't operate on std_logic_vector. So, you need to implement type conversions on your std_logic_vector signals

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

If you definitely wanted to use the "mod" and "rem" operators:

They are not defined in any of the packages that you are using.

FIX: use ieee.numeric_std.all package

mod and rem don't operate on std_logic_vector. So, you need to implement type conversions on your std_logic_vector signals

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

edited Nov 20 '18 at 11:48

answered Nov 20 '18 at 11:06

Sai Varun

854

answered Nov 20 '18 at 11:06

Sai Varun

854

answered Nov 20 '18 at 11:06

Sai Varun

854

1

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

add a comment |

1

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

mod and rem operate on unsigned and signed types, too.

– Matthew Taylor
Nov 20 '18 at 11:27

I added the use iee.numeric_std.all package but now I get other error : signal number : unsigned(5 downto 0):="010111"; -- this is 23 in binary form

– Tomer Polski
Nov 20 '18 at 15:00

That sounds like you need to ask another question.

– Matthew Taylor
Nov 21 '18 at 11:24

add a comment |

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